Functional description

STB5701

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4.2.4

Loop filter

An external PLL loop filter is connected to pin LF (PIN 8). The loop filter controls the

dynamic behavior of the PLL, primarily lock time and reference spur levels. Generally, the

PLL lock time is a small fraction of the overall receiver start-up time. The crystal oscillator is

the largest contributor to start-up time.

4.3

Receiver section

The integrated receiver is intended to be used as a single-conversion FSK/ASK receiver. It

consists of a low noise amplifier, mixer, IF filter, limiter, FSK demodulator, a LPF amplifier,

and a data slicer. The received strength signal indicator (RSSI) can be used for fast carrier

sense detection or as amplitude shift keying, (ASK) demodulator.

4.3.1

Low Noise Amplifier (LNA)

Figure 4.

LNA block diagram

The LNA is based on a cascode topology for low-noise, high gain and good reverse

isolation. The LNA output is directly connected to the mixer removing the external output

matching.

It has 2 step gain managed by an internal AGC. This AGC circuit monitors the RSSI output.

The AGC has a hysteresis of ~10dB.

RSSI

Threshold

I2C

(LNA_GAIN)

Clk

Delay

(1) IN_LNA

32

GND_LNA

(2) VCC_LNA

Image Rejection Mixer