ST10R272LT1 datasheet(54/77 Pages) STMICROELECTRONICS

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ST10R272L - ELECTRICAL CHARACTERISTICS

RdCS to Valid Data In

(with RW delay)

t46

–

3 +

–

2TCL - 17

RdCS to Valid Data In

(no RW delay)

t47

–

13 +

–

3TCL - 17

RdCS, WrCS Low Time

(with RW delay)

t48

13 +

–

2TCL - 7+

–ns

RdCS, WrCS Low Time

(no RW delay)

t49

23 +

–

3TCL - 7+

–ns

Data valid to WrCS

t50

10 +

–

2TCL - 10 +

tC –ns

Data hold after RdCS

t51

0–0

–

Data float after RdCS1 2

t52

–

13 +

–

2TCL - 7 +

Address hold after

RdCS, WrCS

t54

10 +

–

2TCL - 10 +

tF –ns

Data hold after WrCS

t56

10 +

–

2TCL - 10 +

tF –ns

1) Output loading is specified using Figure 13 (CL = 5 pF).

2) This delay assumes that the following bus cycle is a multiplexed bus cycle. If next bus cycle

is demultiplexed, refer to demuxultiplexed equivalent AC timing.

Parameter

Symbol

Max. CPU Clock

= 50 MHz

Variable CPU Clock

1/2TCL = 1 to 50 MHz

min.

max.

min.

max.

Table 17 Multiplexed bus

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