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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8580 데이터시트(PDF) 39 Page - Wolfson Microelectronics plc |
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WM8580 데이터시트(HTML) 39 Page - Wolfson Microelectronics plc |
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39 / 103 page  Production Data WM8580 w PD Rev 4.5 February 2008 39 ADC FEATURES ADC HIGH-PASS FILTER DISABLE The ADC digital filters incorporate a digital high-pass filter. By default, this is enabled but can be disabled by setting the ADCHPD register bit to 1. This allows the input to the ADC to be DC coupled. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R29 ADC Control 1 1Dh 4 ADCHPD 0 ADC high-pass filter disable 0 = high-pass filter enabled 1 = high-pass filter disabled Table 29 ADC Functions Register ADC OVERSAMPLING RATE SELECT The internal ADC signal processing operates at an oversampling rate of 128fs for all MCLK:LRCLK ratios. The exception to this is for operation with a 128fs or 192fs master clock, where the internal oversampling rate of the ADC is 64fs. For ADC operation at 96kHz in 256fs or 384fs mode it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversampling rate from 128fs to 64fs. Similarly, for ADC operation at 192kHz in 128fs or 192fs mode it is recommended that the user set the ADCOSR bit to change the oversampling rate from 64fs to 32fs. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R29 ADC Control 1 1Dh 3 ADCOSR 0 ADC oversample rate select 0 = 128/64x oversampling 1 = 64/32x oversampling Table 30 ADC Functions Register ADC MUTE As with the DAC, each ADC channel also has a mute control bit, which mutes the inputs to the ADC. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 AMUTEL 0 ADC Mute select 0 : Normal Operation 1: mute ADC left 1 AMUTER 0 ADC Mute select 0 : Normal Operation 1: mute ADC right R29 ADC Control 1 1Dh 2 AMUTEALL 0 ADC Mute select 0 : Normal Operation 1: mute both ADC channels Table 31 ADC Mute Register |
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