WM8580 datasheet(50/103 Pages) WOLFSON

50 / 103 page

WM8580

Production Data

PD Rev 4.5 February 2008

In master mode the BCLK and LRCLK driving the SAIF interface are generated by the Master Mode

Clock Gen module. The control of this module is described on page 22.

The clock supplied to the Master Mode Clock Gen module can be ADCMCLK, PLLACLK, PLLBCLK,

or MCLK. Selection is automatic and is based on the digital routing configuration. Figure 31 illustrates

the clock configuration and Table 41 gives some examples of clock routing based on digital routing

configuration.

If the digital routing is configured such that the SAIF Transmitter is sourcing the S/PDIF Receiver,

then PLLACLK is automatically selected, and it is recommended that the interface operate in master

mode. However, if the SAIF Transmitter sources something other than the S/PDIF Receiver and the

S/PDIF Receiver is powered up, then the PLLACLK and PLLBCLK are invalid for SAIF operation, so

the choice forced to MCLK (default) or ADCMCLK.

Figure 31 SAIF Interface Clock Configuration

Digital Routing

Configuration

Clock used by SAIF

Master Mode Clock

Generator

Comments

SAIF Tx = S/PDIF RX

PLLACLK

Recommend to operate SAIF in master

mode

SAIF Tx = PAIF RX

MCLK

Set SAIFMS_CLKSEL = 11

Table 42 SAIF Clock Configuration Examples

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R11

SAIF 1

0Bh

7:6

SAIFMS_

CLKSEL

SAIF Master Mode clock source

00 = ADCMCLK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

Table 43 SAIF Master Mode Clock Control

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