ST18952 datasheet(18/67 Pages) STMICROELECTRONICS

18 / 67 page

18/66

ST18952

Bus Switch Unit

The three memory spaces can be extended off-chip through the bus switch unit (BSU)

peripheral. The figure below shows the layout of the D950Core BSU.

Figure 6.1

D950Core Bus Switch Unit

6.1

BSU operation

The BSU recognizes a bus cycle when a bus extension strobe (IBSE, XBSE or YBSE) goes

active. The BSU decodes the address value to determine if an external memory access is

requested on the I, X or Y-bus and generates the appropriate signals on the external bus side.

The BSU generates software wait-states, depending on the setting of the control register.

If more than one external memory access is attempted at one instruction cycle, they are

serviced sequentially in the following order: I-bus, X-bus, Y-bus.

Each external access requires one basic instruction clock cycle (2 CLKIN cycles), extended

by, at least, one wait-state (2 CLKIN cycles). The number of wait-states can be extended,

either by software with the BSU control registers (see Section 6.2), or by hardware with the

DTACK input signal.

D950Core

BUS

SWITCH

UNIT

DTACK

AS-DSP

BSU_CLK

RESET

IRD/XRD/YRD

IWR/XWR/YWR

IBS/XBS/YBS

INTERNAL MEMORI ES

& PERIPHERALS

MEM.

DTACKin

EYRD/DS

EYWR/RD

EIRD/DS

EIWR/RD

EXRD/DS

EXWR/RD

VR02020A

INTERNAL MEMORIES

& PERIPHERALS

INTERNAL MEMORIES

& PERIPHERALS

DEID/DEXD/DEYD

IID/I XD/IYD

IDT_EN

ST18952 데이터시트(PDF) 18 Page - STMicroelectronics

ST18952 데이터시트(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

데이터시트 다운로드

링크 URL