 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
ST20CX 데이터시트(PDF) 73 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST20CX 데이터시트(HTML) 73 Page - STMicroelectronics |
|
|
73 / 212 page  diss 73/212 ® diss disable skip Code: 23 F0 Description: Disable a ‘skip’ guard in an alternative sequence. Areg is the offset from the byte following the altend to the start of the guarded process and Breg is the boolean guard. If this is the first ready guard then the value in Areg is stored in workspace and Areg is set to true, otherwise Areg is set to false. Note that this instruction should be used as part of an alternative sequence following an altwt or taltwt instruction. Definition: if (Breg = false)– boolean guard is false Areg ′← false else if (word[Wptr @ pw.Temp] = NoneSelected.o) Areg ′← false – this is the first ready guard else – another guard was selected { word ′[Wptr @ pw.Temp] ← Areg Areg ′← true } Breg ′← Creg Creg ′← undefined Error signals: none Comments: Secondary instruction. Uses the pw.Temp slot in the process workspace. See also: alt altend altwt enbs talt taltwt |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
