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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST20CX 데이터시트(PDF) 161 Page - STMicroelectronics |
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ST20CX 데이터시트(HTML) 161 Page - STMicroelectronics |
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161 / 212 page  shr 161/212 ® shr shift right Code: 24 F0 Description: Logical shift right Breg by Areg places, filling with z ero bits. If the initial Areg is not between 0 and 31 inclusive then the result is zero. The result is only defined for shift lengths less than the word length. Definition: if (0 ≤ Areg < BitsPerWord) Areg ′← Breg >> Areg else Areg ′← undefined Breg ′← Creg Creg ′← undefined Error signals: none Comments: Secondary instruction. The behavior for shift lengths the outside stated range is implementation dependent. See also: lshl lshr norm shl |
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