ST7265X datasheet(94/166 Pages) STMICROELECTRONICS

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ST7265x

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PWM/BRM GENERATOR (Cont’d)

BRM Generation

The BRM bits allow the addition of a pulse to wid-

en a standard PWM pulse for specific PWM cy-

cles. This has the effect of “fine-tuning” the PWM

Duty cycle (without modifying the base duty cycle),

thus, with the external filtering, providing additional

fine voltage steps.

The incremental pulses (with duration of TCPU) are

added to the beginning of the original PWM pulse.

The PWM intervals which are added to are speci-

fied in the 4-bit BRM register and are encoded as

shown in the following table. The BRM values

shown may be combined together to provide a

summation of the incremental pulse intervals

specified.

The pulse increment corresponds to the PWM res-

olution.

For example,if

– Data 18h is written to the PWM register

– Data 06h (00000110b) is written to the BRM reg-

ister

– with a 8MHz internal clock (125ns resolution)

Then 3.0

µs-long pulse will be output at 8 µs inter-

vals, except for cycles numbered 2,4,6,10,12,14,

where the pulse is broadened to 3.125

µs.

Note. If 00h is written to both PWM and BRM reg-

isters, the generator output will remain at “0”. Con-

versely, if both registers hold data 3Fh and 0Fh,

respectively, the output will remain at “1” for all in-

tervals 1 to 15, but it will return to zero at interval 0

for an amount of time corresponding to the PWM

resolution (TCPU).

An output can be set to a continuous “1” level by

clearing the PWM and BRM values and setting

POL = “1” (inverted polarity) in the PWM register.

This allows a PWM/BRM channel to be used as an

additional I/O pin if the DAC function is not re-

quired.

Table 30. Bit BRM Added Pulse Intervals

(Interval #0 not selected).

Figure 55. BRM pulse addition (PWM > 0)

BRM 4 - Bit Data

Incremental Pulse Intervals

0000

none

0001

i = 8

0010

i = 4,12

0100

i = 2,6,10,14

1000

i = 1,3,5,7,9,11,13,15

CPU x 64

CPU x 64 increment

m = 1

m = 0

m = 2

CPU x 64

m = 15

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