ST7265X datasheet(29/166 Pages) STMICROELECTRONICS

부품명	ST7265X

상세설명	LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI

PDF	166 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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ST7265x

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6.2 RESET SEQUENCE MANAGER (RSM)

6.2.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 6.2.2:

External RESET source pulse

Internal LVD RESET (Low Voltage Detection)

Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 18:

Active Phase depending on the RESET source

Min 512 CPU clock cycle delay (see Figure 20

and Figure 21

RESET vector fetch

Figure 18. RESET Sequences

VDD

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

VIT+(LVD)

VIT-(LVD)

th(RSTL)in

tw(RSTL)out

RUN

th(RSTL)in

ACTIVE

WATCHDOG UNDERFLOW

tw(RSTL)out

RUN

RESET

SOURCE

SHORT EXT.

RESET

LVD

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTERNAL RESET (min 512 TCPU)

VECTOR FETCH

tw(RSTL)out

PHASE

ACTIVE

PHASE

ACTIVE

PHASE

DELAY

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