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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7265X 데이터시트(PDF) 31 Page - STMicroelectronics |
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ST7265X 데이터시트(HTML) 31 Page - STMicroelectronics |
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31 / 166 page  ST7265x 31/166 RESET SEQUENCE MANAGER (Cont’d) In stand-alone mode, the 512 CPU clock cycle de- lay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. In USB mode the delay is 256 clock cycles count- ed from when the PLL LOCK signal goes high. The RESET vector fetch phase duration is 2 clock cycles. Figure 20. Reset Delay in Stand-alone Mode Figure 21. Reset Delay in USB Mode Note: For a description of Stand-alone mode and USB mode refer to Section 6.4. 512 x tCPU(STAND-ALONE) RESET FETCH VECTOR DELAY FETCH VECTOR 256 x tCPU(STAND-ALONE) 256 x tCPU(USB) PLL Startup RESET time (undefined) DELAY 400 µs typ. 1 |
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