 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
ST7265X 데이터시트(PDF) 113 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST7265X 데이터시트(HTML) 113 Page - STMicroelectronics |
|
|
113 / 166 page  ST7265x 113/166 I²C SINGLE MASTER BUS INTERFACE (Cont’d) 11.7.5 Low Power Modes 11.7.6 Interrupts Figure 69. Event Flags and Interrupt Generation Note: The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bits in the CC register are reset (RIM instruction). Mode Description WAIT No effect on I2C interface. I2C interrupts cause the device to exit from WAIT mode. HALT I2C registers are frozen. In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt End of Byte Transfer Event BTF ITE Yes No Start Bit Generation Event (Master mode) SB Yes No Acknowledge Failure Event AF Yes No BTF SB AF EVF INTERRUPT ITE * * EVF can also be set by EV2 or an error from the SR2 register. * |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
