DSP56F826 datasheet(34/60 Pages) FREESCALE

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56F827 Technical Data, Rev. 12

Freescale Semiconductor

Input Data Hold to RD Deasserted

tDRD

0—

RD Assertion Width

Wait states = 0

Wait states > 0

tRD

(T*WS) + 19

—

Address Valid to Output Data Valid

Wait states = 0

Wait states > 0

tAD

—

(T*WS) + 1

Address Valid to RD Asserted

tARDA

-4.4

—

RD Asserted to Input Data Valid

Wait states = 0

Wait states > 0

tRDD

—

2.4

(T*WS) + 2.4

WR Deasserted to RD Asserted

tWRRD

6.8

—

RD Deasserted to RD Asserted

tRDRD

0—

WR Deasserted to WR Asserted

tWRWR

14.1

—

RD Deasserted to WR Asserted

tRDWR

12.8

—

1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and

T = Clock Period. For 80MHz operation, T = 12.5ns.

2. Parameters listed are guaranteed by design.

To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:

Top = Clock period @ desired operating frequency

WS = Number of wait states

Memory Access Time = (Top*WS) + (Top- 11.5)

Table 3-10 External Bus Asynchronous Timing1, 2 (Continued)

Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic

Symbol

Min

Max

Unit

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