DSP56F826 datasheet(19/60 Pages) FREESCALE

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Signals and Package Information

56F827 Technical Data, Rev. 12

Freescale Semiconductor

IRQB

Input

(Schmitt)

External Interrupt Request B—The IRQB input is an external interrupt

request that indicates that an external device is requesting service. It can be

programmed to be level-sensitive or negative-edge-triggered. If level-sensitive

triggering is selected, an external pull-up resistor is required for wired-OR

operation.

RESET

Input

(Schmitt)

Reset—This input is a direct hardware reset on the processor. When RESET

is asserted low, the device is initialized and placed in the Reset state. A

Schmitt trigger input is used for noise immunity. When the RESET pin is

deasserted, the initial chip operating mode is latched from the external boot

pin. The internal reset signal will be deasserted synchronous with the internal

clocks, after a fixed number of internal clocks.

To ensure complete hardware reset, RESET and TRST should be asserted

together. The only exception occurs in a debugging environment when a

hardware device reset is required and it is necessary not to reset the

OnCE/JTAG module. In this case, assert RESET, but do not assert TRST.

EXTBOOT

Input

(Schmitt)

External Boot—This input is tied to VDD to force device to boot from off-chip

memory. Otherwise, it is tied to VSS.

Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)

Signal Name

Pin No.

Type

Description

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