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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT89C51ID2-RDTIM 데이터시트(PDF) 91 Page - ATMEL Corporation |
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AT89C51ID2-RDTIM 데이터시트(HTML) 91 Page - ATMEL Corporation |
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91 / 159 page  91 AT89C51ID2 4289A–8051–09/03 Figure 35. Format and State in the Slave Receiver Mode SSLA WA Data A Data P or S A P or S A General Call A Data A Data P or S A A 60h 68h 80h 80h A0h 88h 70h 90h 90h A0h P or S A 98h A 78h Data A n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the 2-wire bus Reception of the own slave address and one or more data bytes. All are acknowledged. Last data byte received is not acknowledged. Arbitration lost as master and addressed as slave Reception of the general call address and one or more data bytes. Last data byte received is not acknowledged. Arbitration lost as master and addressed as slave by general call |
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