AT89C51ID2-RDTIM datasheet(16/159 Pages) ATMEL

16 / 159 page

AT89C51ID2

4289A–8051–09/03

Table 16. OSCCON Register

OSCCON- Oscillator Control Register (86h)

Reset Value = XXXX X0’HSB.OSC’’HSB.OSC’b (see Hardware Security Byte (HSB))

Not bit addressable

Table 17. CKRL Register

CKRL - Clock Reload Register

Reset Value = 1111 1111b

Not bit addressable

7654

3210

-----

SCLKT0

OscBEn

OscAEn

Bit

Number

Bit

Mnemonic

Description

Reserved

2SCLKT0

Sub Clock Timer0

Cleared by software to select T0 pin

Set by software to select T0 Sub Clock

Cleared by hardware after a Power Up

OscBEn

OscB enable bit

Set by software to run OscB

Cleared by software to stop OscB

Programmed by hardware after a Power-up regarding HSB.OSC (Default

cleared, OSCB stopped)

OscAEn

OscA enable bit

Set by software to run OscA

Cleared by software to stop OscA

Programmed by hardware after a Power-up regarding HSB.OSC(Default Set,

OSCA runs)

7654

3210

--------

Bit

Number

Mnemonic

Description

7:0

CKRL

Clock Reload Register:

Prescaler value

AT89C51ID2-RDTIM 데이터시트(PDF) 16 Page - ATMEL Corporation

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