ADE7166ASTZF8 datasheet(42/148 Pages) AD

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ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 42 of 148

CF2

Logic one indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse

output is not enabled by clearing bit 2 of MODE1 register.

CF1

Logic one indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse

output is not enabled by clearing bit 1 of MODE1 register.

VAEOF

Logic one indicates that the VAHR register has overflowded

REOF11

Logic one indicates that the VARHR register has overflowded

AEOF

Logic one indicates that the WATTHR register has overflowded

VAEHF

Logic one indicates that the VAHR register is half full

REHF1

Logic one indicates that the VARHR register is half full

AEHF

Logic one indicates that the WATTHR register is half full

Table 38. Interrupt Status Register 3 SFR (MIRQSTH, 0xDE)

Bit

Location

Interrupt Flag

Description

RESET

Indicates the end of a reset (for both sofware or hardware reset).

Reserved

WFSM

Logic one indicates that new data is present in the Waveform Registers

PKI

Logic one indicates that current channel has exceeded the IPKLVL value

PKV

Logic one indicates that voltage channel has exceeded the VPKLVL value.

CYCEND

Logic one indicates the end of the energy accumulation over an integer number of half

line cycles.

ZXTO

Logic one indicates that no zero crossing on the line voltage happened for the last

ZXTOUT half line cycles.

Logic one indicates detection of a zero crossing in the voltage channel.

Table 39. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9)

Bit

Location

Interrupt Flag

Description

7-6

Reserved

Reserved.

FAULTSIGN12

When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052

core.

VARSIGN1

When this bit is set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core.

APSIGN

When this bit is set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core.

VANOLOAD

When this bit is set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052

core.

RNOLOAD1

When this bit is set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052

core.

APNOLOAD

When this bit is set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052

core.

Table 40. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA)

Bit

Location

Interrupt Flag

Description

CF2

When this bit is set, a CF2 pulse issued creates a pending ADE interrupt to the 8052 core.

CF1

When this bit is set, a CF1 pulse issued creates a pending ADE interrupt to the 8052 core.

VAEOF

When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.

REOF1

When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core.

AEOF

When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core.

VAEHF

When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.

REHF1

When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core.

11 This function is not available in ADE7566 and ADE7166 products.

12 This function is not available in ADE7566 and ADE7569 products.

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