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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADE7166ASTZF8 데이터시트(PDF) 13 Page - Analog Devices |
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ADE7166ASTZF8 데이터시트(HTML) 13 Page - Analog Devices |
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13 / 148 page  Preliminary Technical Data ADE75xx/ADE71xx Rev. PrE | Page 13 of 148 Table 4. SPI MASTER MODE TIMING (CPHA = 1) Parameter Min Typ Max Unit tSL SCLOCK Low Pulse Width1 977 ns tSH SCLOCK High Pulse Width1 977 ns tDAV Data Output Valid after SCLOCK Edge TBD ns tDSU Data Input Setup Time before SCLOCK Edge TBD ns tDHD Data Input Hold Time after SCLOCK Edge TBD ns tDF Data Output Fall Time 10 25 ns tDR Data Output Rise Time 10 25 ns tSR SCLOCK Rise Time 10 25 ns tSF SCLOCK Fall Time 10 25 ns ____________________________________________ 1 Characterized under the following conditions: a. Core clock divider bits CD2, CD1, and CD0 in POWCON SFR set to 0, 0, and 0, respectively, that is, core clock frequency = 4.096/8 MHz. b. SPI bit-rate selection bits SPIR1 and SPR0 in SPI2CMOD SFR set to 0 and 0, respectively. SCLOCK (CPOL = 0) t DSU SCLOCK (CPOL = 1) MOSI MISO MSB LSB LSB IN BITS 6–1 BITS 6–1 t DHD t DR t DAV t DF t SH t SL t SR t SF MSB IN Figure 4. SPI Master Mode Timing (CPHA = 1) |
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