C167CS datasheet(59/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-9

V2.0, 2000-07

BUSCON/ADDRSEL

The instruction following an instruction that changes the properties of an external

address area cannot access operands within the new area. In these cases an instruction

that does not access this address area should be inserted. Code accesses to the new

address area should be made after an absolute branch to this area.

Note: As a rule, instructions that change external bus properties should not be executed

from the respective external memory area.

Timing

Instruction pipelining reduces the average instruction processing time in a wide scale

(from four to one machine cycles, mostly). However, there are some rare cases, where

a particular pipeline situation causes the processing time for a single instruction to be

extended either by a half or by one machine cycle. Although this additional time

represents only a tiny part of the total program execution time, it might be of interest to

avoid these pipeline-caused time delays in time critical program modules.

Besides a general execution time description, Section 4.3 provides some hints on how

to optimize time-critical program parts with regard to such pipeline-caused timing

particularities.

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