C167CS datasheet(119/517 Pages) INFINEON

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C167CS

Derivatives

Clock Generation

User’s Manual

6-1

V2.0, 2000-07

Clock Generation

All activities of the C167CS’s controller hardware and its on-chip peripherals are

controlled via the system clock signal

fCPU.

This reference clock is generated in three stages (see also Figure 6-1):

Oscillator

The on-chip Pierce oscillator can either run with an external crystal and appropriate

oscillator circuitry or it can be driven by an external oscillator or another clock source.

Frequency Control

The input clock signal feeds the controller hardware:

• directly, providing phase coupled operation on not too high input frequency

• divided by 2 in order to get 50% duty cycle clock signal

• via an on-chip phase locked loop (PLL) providing max. performance on low input

frequency

• via the Slow Down Divider (SDD) in order to reduce the power consumption.

The resulting internal clock signal is referred to as “CPU clock”

fCPU.

Clock Drivers

The CPU clock is distributed via separate clock drivers which feed the CPU itself and

two groups of peripheral modules. The RTC is fed with the prescaled oscillator clock

(

fRTC) via a separate clock driver, so it is not affected by the clock control functions.

Figure 6-1

CPU Clock Generation Stages

MCD04457

OSC

Prescaler

PLL

SDD

Idle Mode

CPU

PCDDIS

Peripherals,

Ports, Intrl. Ctrl.

Interfaces

CCD

PCD

ICD

P. D. Mode

RTC

32:1

Oscillator

Frequency Control

Clock Drivers

RTC

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