C167CS-L datasheet(20/81 Pages) INFINEON

20 / 81 page

C167CS-4R

C167CS-L

Data Sheet

V2.2, 2001-08

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus

Controller (EBC). It can be programmed either to Single Chip Mode when no external

memory is required, or to one of four different external memory access modes, which are

as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/

output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses

and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,

Memory Tri-State Time, Length of ALE and Read Write Delay) have been made

programmable to allow the user the adaption of a wide range of different types of

memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via register pairs

ADDRSELx / BUSCONx) which control the access to different resources with different

bus characteristics. These address windows are arranged hierarchically where

BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to

locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 5 external CS signals (4 windows plus default) can be generated in order to save

external glue logic. The C167CS offers the possibility to switch the CS outputs to an

unlatched mode. In this mode the internal filter logic is switched off and the CS signals

are directly generated from the address. The unlatched CS mode is enabled by setting

CSCFG (SYSCON.6).

Access to very slow memories or memories with varying access times is supported via

a particular ‘Ready’ function.

A HOLD/HLDA protocol is available for bus arbitration and allows to share external

resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN

in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ, HLDA, HOLD)

are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA

pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA

is switched to input. This allows to directly connect the slave controller to another master

controller without glue logic.

For applications which require less than 16 MBytes of external memory space, this

address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case

Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an

address space of 16 MBytes is used.

C167CS-L 데이터시트(PDF) 20 Page - Infineon Technologies AG

C167CS-L 데이터시트(HTML) 20 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

데이터시트 다운로드

링크 URL