40 / 98 page
CybraTech (2000) Ltd.
SOC-3000/i Scale-On-Chip
ASIC
Technical Specification
Revision B
Page 32
July, 2002
Controller Registers
Keyboard controller interface includes a control register (one byte) and a data/status
register (two bytes).
The Keyboard controller registers are defined in Table 13.
TABLE 13: KEYBOARD CONTROLLER REGISTERS DESCRIPTION
FUNCTION
ADDRESS
BIT
REMARKS
Controller Clock Enable
C200H
2
1= Enable
0= Disable
Controller RESET
C400H
All
0xFF = Reset
Data Registers
F100H to F101H
All
Read only
Control Register
F100H
All
Write only
Registers Description
Control Register
The keyboard control register bit definitions, functions, and settings are displayed in
Table 14.
TABLE 14: KEYBOARD CONTROLLER CONTROL REGISTER BIT FUNCTIONS
ADDRESS
BIT
FUNCTION
SETTINGS
0-2
(bit 0 -LSB)
Anti-Bounce Timeout
000 = 4 ms
001 = 6 ms
010 = 8 ms
011 = 10 ms
100 = 12 ms
101 = 14 ms
110 = 16 ms
111 = 18 ms
3
Interrupt Enable/Disable
0 = Enable
1 = Disable (default)
F100H
4-7
Don’t Care
Don’t Care
Data Registers
Keyboard data is stored in two 8-bit registers.
The data register bit functions are shown in Table 15.
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
