CybraTech (2000) Ltd.
SOC-3000/i Scale-On-Chip
ASIC
Technical Specification
Revision B
Page iv
July, 2002
LIST OF FIGURES
FIGURE 1:
SOC-3000 TYPICAL APPLICATION ........................................................................................ 1
FIGURE 2:
SOC-3000 BLOCK DIAGRAM................................................................................................. 2
FIGURE 3:
MECHANICAL OUTLINE DRAWING ........................................................................................ 6
FIGURE 4:
MAIN BOARD PADS DIMENSIONS RECOMMENDATION ........................................................ 7
FIGURE 5:
SOC-3000 PIN ARRANGEMENT ........................................................................................... 15
FIGURE 6:
SOC-3000 LCD DISPLAY PIN CONFIGURATION ................................................................. 16
FIGURE 7:
SOC-3000 LED DISPLAY PIN CONFIGURATION ................................................................. 17
FIGURE 8:
CPU BLOCK DIAGRAM........................................................................................................ 21
FIGURE 9:
SOC-3000 PROGRAM MEMORY MAP.................................................................................. 22
FIGURE 10:
SOC-3000/I STARTUP PROCEDURE .................................................................................... 24
FIGURE 11:
SOC-3000 DATA MEMORY MAP......................................................................................... 25
FIGURE 12:
KEYBOARD MATRIX CONFIGURATION ................................................................................ 31
FIGURE 13:
LCD CONTROLLER/DRIVER BLOCK DIAGRAM ................................................................... 35
FIGURE 14:
STATIC DRIVE MODE WAVEFORMS..................................................................................... 37
FIGURE 15:
1:2 MULTIPLEX DRIVE RATIO–1/2 BIAS WAVEFORMS....................................................... 38
FIGURE 16:
1:2 MULTIPLEX DRIVE RATIO–1/3 BIAS WAVEFORMS....................................................... 39
FIGURE 17:
1:3 MULTIPLEX DRIVE RATIO WAVEFORMS....................................................................... 40
FIGURE 18:
1:4 MULTIPLEX DRIVE RATIO WAVEFORMS....................................................................... 41
FIGURE 19:
BACKPLANE OUTPUTS PER LCD DIGIT ............................................................................... 43
FIGURE 20:
LED PARALLEL DISPLAY CONTROLLER BLOCK DIAGRAM ................................................ 45
FIGURE 21:
LED PARALLEL DISPLAY CONTROLLER TIMING DIAGRAM ............................................... 46
FIGURE 22:
LED SERIAL INTERFACE DISPLAY BLOCK DIAGRAM ......................................................... 49
FIGURE 23:
LED SERIAL INTERFACE CONTROLLER TIMING DIAGRAM................................................. 50
FIGURE 24:
CLOCK GENERATOR BLOCK DIAGRAM ............................................................................... 55
FIGURE 25:
LOW VOLTAGE DETECTOR .................................................................................................. 59
FIGURE 26:
4-WIRE LOAD-CELL CONNECTION ...................................................................................... 76
FIGURE 27:
6-WIRE LOAD-CELL CONNECTION ...................................................................................... 76
FIGURE 28:
MULTIPLE LOAD-CELL CONNECTION.................................................................................. 77
FIGURE 29:
KEYBOARD INTERFACE ....................................................................................................... 78
FIGURE 30:
LCD DISPLAY INTERFACE................................................................................................... 79
FIGURE 31:
LED PARALLEL DISPLAY INTERFACE ................................................................................. 80
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