STLC5445

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RGND

Ground connection of the relay drivers.

CKILC

Logic input.

External clock input for the Power On Sequencer embedded in the Logic interface (see the

block diagram at page 3). The Power On Sequencer controls (if activated) the power on se-

quence of the lines. This will limit the chip's temperature increase that occurs, at channels

switch on, due to the charging current of the capacitances used by the external ISDN circuitry.

If used, the Power on sequencer is the only block of the circuit that needs an external clock sig-

nal.

ESn (n=0-3)

Logic inputs.

These pins have double names (see the block diagram at page 3) because they perform a dou-

ble function: one in Parallel mode ( PSC = 0 ), and another in MPI mode ( PSC = 1).

In Parallel mode ESn acts as an activation or deactivation request for the respective line driver:

ESn = 0: Line driver deactivation request.

ESn = 1: Line driver activation request.

In MPI mode the pins perform the following functions:

A0:

Selects the source and destination locations for read and write operations on the

data bus. A0 must be valid on the falling edge of ALE or during RDN and WRN

if ALE is tied High. Data transfer occurs over the D0-D3 lines.

CSN:

This pin acts as a chip select. It must be Low to enable the read or write opera-

tions of the device.

RDN:

Read command. The active Low read signal is conditioned by CSN and trans-

fers internal information to the data bus. If A0 is a logical 0, the logic levels of

the Indirect Address Register (IAR) and of the Thermal Shutdown Status bit will

be transferred to D3-D0. If A0 is a logical 1, the data addressed by the IAR will

be transferred to D3-D0.

WRN:

Write command. The active Low write signal is conditioned by CSN and trans-

fers information from the data bus to one of the two internal registers selectable

by A0: if A0 is a logical 1, D3-D0 is written into the Line Enable Register (LER);

if A0 is a logical 0, D2-D0 are written into the Indirect Address Register (IAR)

and D3 is written as bit 3 and manages the generation of the interrupt signal for

the external microprocessor. LER and IAR are the only two writable registers in

the device.

RESETN

Reset pin. It initializes the Power on sequencer, the TOR register and, in the MPI interface, the

registers and the INTN (interrupt output pin). When applied it leaves all the line drivers switched

off.

It has no effect in Parallel interface mode if the power on sequencer is not used.

When the supply voltages are applied to the circuit, an equivalent RESETN pulse (power on

reset) is automatically, internally generated.

ALE

Address Latch Enable. ALE is a logic input pin. It is used to strobe the address bit applied at

the A0 pin, into the address latch. The address is latched on the High to Low transition of ALE.

While ALE is High the address latch is transparent. For a non multiplexed microprocessor bus,

ALE must be tied High.

ILIM

The current limiting programming input, ILIM, is used to program the current limit of the four

drivers by means of an external resistor connected between this pin and DGND. The voltage at

ILIM pin is a replica of the internal bandgap voltage (1.236V).

When a line driver is in current limitation, its output current is 2155 times higher than the current

flowing in the external current limiting programming resistor.

INTN

The INTN (interrupt) open drain type output can only be used in MPI interface mode. INTN can

be used to alerts an external microprocessor when a current overload condition occurs. It is not