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STLC5445

Each of the four channels generates two status detector bits (see the block diagram at page 3): the COD bit

(Current Overload Detector) and the OLD bit (Open Loop Detector). The functions of the two bits are the follow-

ing:

The COD bit goes in a High logic state when its channel is in current limiting condition. Since in

the ISDN application it can happens that the sum of the DC line current and the superimposed

signal peaks, easily exceeds the needed DC current limit, the COD generation circuitry has

been arranged in such a way that the COD bit will be pushed High only if the current overload

persists for at least 20ms: this eliminates any spurious High level COD. The mentioned delaying

function requires, for each of the four channels, one Capacitor of 100nF has to be connected

between each CODCn and ground.

The OLD bit goes in a High state logic when the current that the channel supplies to the line

falls below a typical value of 3mA, indicating a probable open line condition.

As explained in the following pages, when operating in MPI mode the COD and OLD bits can, for each of the

four channels, be red by an external microprocessor in order to check which channel (if any) is over or under

loaded. When in Parallel mode a single status bit (the NACKn bit) is provided for each channel and is directly

available on a dedicated pin. The NACKn bit is internally generated by OR combining the COD bit with two other

bits (see the Logic section for a more detailed explanation).

Logic Section

The Logic section comprises the Parallel interface, the MPI interface and the Power on sequencer. In the

block diagram shown at page 3 the three functions have been condensed in a single entity: the Logic interface

block.

For each of the four channels, both types of the two provided interfaces use the COD, OLD and TOR (Thermal

Overload Register) status detector bits:

The COD (Current Overload Detector) bit is in a High logic state when its channel is in current

limiting condition since at least 20ms.

The OLD (Open Loop Detector) bit is in a High logic state when the current that the channel

supplies to the line falls below a typical value of 3mA (ISOC spec's parameter), indicating a pos-

sible open line condition.

Each of the four output line drivers can be switched on, only if their corresponding TOR bit is

High.

The TOR bits are automatically set High by the internal power on reset when the chip is initially

connected to its power supplies but can, however, also be globally set High by applying a reset

pulse to the RESETN pin. Alternatively the TOR bits that are latched in a Low state can individ-

ually be set High by applying to the selected interface the switch off command relative to their

channel.

The TOR bits will go in a Low state (determining the shut off of their relative channel's driver) in

two cases:

The activated channel is in current limiting condition and the chip's temperature reaches 130°C.

In this case the TOR will be latched in Low state.

The chip's temperature reaches 160°C: in this case the TOR bits will all be set Low but only the

TOR of the activated channels will be latched.

Power on sequencer

When activated (PBIT pin Low), the Power on sequencer manages the channels' activation requests received

through the Parallel (PSC pin Low) or the MPI (PSC pin High) interface. The incoming channels' activation re-

quests are stored in the Power on sequencer and then satisfied, one at a time, only when the previously acti-

vated channel exit the current limiting condition that normally occurs at power on, due to the capacitive element

that is part of the ISDN load. It must be noted that once a channel exits from the channel's turn on current limiting

phase, the fact that it can for example because of a new line overload fall again in a current limiting condition