STLC5445

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has no influence in the activation sequence of the next channels. The stored activation requests are satisfied

starting from the lower index of the actually stored requests: if (for example) while channel 2 is in the activation

phase, additional power on requests arrive for (in the order) channels 1, 3 and 0, when the channel's 2 activation

phase will be concluded the stored activation requests will be satisfied in the order 0, 1 and 3. It must be noted

that the channels' deactivation requests are not conditioned by the Power on sequencer.

Figure 7. Power on sequence example

Notes: DARn are the line Drivers' Activation Request bits sent to the Power on sequencer. They are internally generated starting from the

activation requests coming from the outside world through the selected interface (Parallel or MPI). POFn are the Power On Flags.

Each POFn goes High with its relative DARn bit and returns to a Low state when the current limiting condition ends: a POF High state

indicates that the relative channel is in the power on phase.

The figure 6 shows, for three of the four available channels, a typical power on sequence example. The CODn

pulse duration represents the time needed to charge the capacitive element that is part of the ISDN load, with

part of the constant current that each line driver provides with the actually programmed current limiting value. It

must be realized that if (for example) has been required the activation of the lines 0, 2 and 3 but line 2 is over-

loaded and cannot leave the current limiting condition, the activation sequence will remain blocked at the line 2

activation step. In this case the external software has to identify and shut off the overloaded line in order to allow

the activation of the line 3.

The previously mentioned RESETN pin will also influence the Power on sequencer: when RESETN is pushed

Low the Power on sequencer is reset, switching off the actually activated drivers.

The Power on sequencer is the only block of the circuit that needs an external clock signal to be applied at the

CKILC pin. The clock frequency is not critical and has a nominal value of 8kHz.

When PBIT=1 the power on sequencer is disabled and the incoming channels' activation requests will instan-

taneously be satisfied. In this case the user as to take into account the actual operative condition (VBAT, the

programmed current limiting value, the load applied to the lines, the ambient temperature) and implement his

own power on sequence in order to limit the chip's temperature increase induced by the channels' switch on

transients.

DAR0

COD0

POF0

DAR1

COD1

POF1

DAR2

COD2

POF2