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TDA7505 데이터시트(PDF) 22 Page - STMicroelectronics |
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TDA7505 데이터시트(HTML) 22 Page - STMicroelectronics |
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22 / 38 page ![]() Electrical specifications TDA7505 22/38 4.10 DRAM/SRAM interface (EMI) 4.11 Debug port interface tF Fall time of both SDA and SCL signals Cb in pF – 300 20+0.1Cb 300 ns tSU;STO Set-up time for STOP condition 4 – 0.6 – ms tSU:DAT Data set-up time 250 – 100 – ns Cb Capacitive load for each bus line – 400 – 400 pF Table 15. I2C Timing (continued) Symbol Parameter Test condition Standard mode I2C bus Fast mode I2C bus Unit Min. Max. Min. Max. Table 16. DRAM timing Symbol Parameter Test condition Min. Typ. Max. Unit Tacc0 Fast DRAM access time EDTM=0, 16 bit word 17 Tdsp Tacc0 Fast DRAM access time EDTM=0, 24 bit word 23 Tdsp Tacc1 Slow DRAM access time EDTM=1, 16 bit word 24 Tdsp Tacc1 Slow DRAM access time EDTM=1, 24 bit word 32 Tdsp Table 17. DRAM refresh period Symbol Parameter Test condition Min. Typ. Max. Unit Tref DRAM refresh period 469 782 Tdsp Table 18. SRAM Timing Symbol Parameter Test condition Min. Typ. Max. Unit Tacc SRAM access time 2 9 Tdsp Table 19. Debug port interface No. Characteristics (Fdsp = 75MHz) Min. Max. Unit 1 DBCK rise time 2 ns 2 DBCK fall time 2 ns 3 DBCK low 40 ns 4 DBCK high 40 ns 5 DBCK cycle time 200 ns 6 DBRQN asserted to DBOUT (ACK) asserted 5*TDSP ns 7 DBCK high to DBOUT valid 40 ns |
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