OR4 datasheet(30/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Embedded Block RAM (continued)

Table 10. Constant Multiplier Signals

Table 11. 8x8 Multiplier Signals

Table 12. CAM Signals

Port Signals

I/O

Function

AR0[15:0]

Data input–operand.

AW(1:0)[8:0]

Address bits.

D(1:0)[17:0]

Data inputs to load memory or change coefﬁcient.

CKW[0:1]

Positive-edge write port clock.

CKR[0:1]

Positive-edge read port clock. Used for synchronous multiply mode.

CSW[1:0]

Active-high write enable.

CSR[1:0]

Active-high read enable.

Q[23:0]

Data outputs–product result.

Port Signals

I/O

Function

AR0[7:0]

Data input-Multiplicand.

AR1[7:0]

Data input-Multiplier.

CKR[0:1]

Positive-edge read port clock. Used for synchronous multiply mode.

CSR[1:0]

Active-high read enable.

Q[15:0]

Data outputs-product.

Port Signals

I/O

Function

AR(1:0)[7:0]

Data Match.

AW(1:0)[8:0]

Data Write.

D(1:0)[17]

Clear data active high.

D(1:0)[16]

Single match active high.

D(1:0)[3:0]

CAM address for data write.

CSW[1:0]

Active-high write enable. Enable for CAM data write.

CSR[1:0]

Active-high read enable. Enable for CAM data match.

Q(1:0)15:0]

Decoded Data outputs. “1” corresponds to a data match at that address location.

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