OR4 datasheet(33/152 Pages) LATTICE

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Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Programmable Input/Output Cells (continued)

Table 13. Series 4 Programmable I/O Standards

Note: interfaces to DDR and ZBT memories are supported through the interface standards shown above.

The PIOs are located along the perimeter of the device. The PIO name is represented by a two-letter designation to

indicate the side of the device on which it is located followed by a number to indicate the row or column in which it is

located. The ﬁrst letter, P, designates that the cell is a PIO and not a PLC. The second letter indicates the side of the

array where the PIO is located. The four sides are left (L), right (R), top (T), and bottom (B). A number follows to

indicate the PIC row or column. The individual I/O pad is indicated by a single letter (either A, B, C, or D) placed at

the end of the PIO name. As an example, PL10A indicates a pad located on the left side of the array in the tenth

row.

Each PIC interfaces to four bond pads through four PIOs and contains the necessary routing resources to provide

an interface between I/O pads and the CIBs. Each PIC contains input buffers, output buffers, routing resources,

latches/FFs, and logic and can be conﬁgured as an input, output, or bidirectional I/O. Any PIO is capable of sup-

porting the I/O standards listed in Table 13.

The CIBs that connect to the PICs have signiﬁcant local routing resources, similar to routing in the PLCs. This new

routing increases the ability to ﬁx user pinouts prior to placement and routing of a design and still maintain routabil-

ity. The ﬂexibility provided by the routing also provides for increased signal speed due to a greater variety of optimal

signal paths.

Included in the routing interface is a fast path from the input pins to the PFU logic. This feature allows for input sig-

nals to be very quickly processed by the SLIC decoder function and used on-chip or sent back off of the FPGA.

A diagram of a single PIO is shown in Figure 22, and Table 14 provides an overview of the programmable functions

in an I/O cell.

Standard

VDDIO (V)

VREF (V)

Interface Usage

LVTTL

3.3

General purpose.

LVCMOS2

2.5

LVCMOS18

1.8

PCI

3.3

PCI.

LVDS

2.5

Point to point and multi-drop backplanes, high noise immunity.

Bused-LVDS

2.5

Network backplanes, high noise immunity, bus architecture

backplanes.

LVPECL

3.3

Network backplanes, differential 100 MHz+ clocking, optical

transceiver, high-speed networking.

PECL

3.3

2.0

Backplanes.

GTL

3.3

0.8

Backplane or processor interface.

GTL+

3.3

1.0

HSTL-class I

1.5

0.75

High-speed SRAM and networking interfaces.

HTSL-class III and IV

1.5

0.9

STTL3-class I and II

3.3

1.5

Synchronous DRAM interface.

SSTL2-class I and II

2.5

1.25

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