STA323W datasheet(15/77 Pages) STMICROELECTRONICS

15 / 77 page

STA323W

Pin out

15/77

3.2

Pin description

OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3)

The half-bridge PWM outputs 1A, 1B, 2A and 2B provide the inputs signals to the speakers.

RESET (pin 22)

Driving RESET low sets all outputs low and returns all register settings to their default

(reset) values. The reset is asynchronous to the internal clock.

SDA, SCL (pins 24, 23)

The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification

(See Chapter 6 on page 33.) Fast-mode (400 kB/s) I2C communication is supported.

VDDA, GNDA (pins 29,28)

The phase locked loop power is applied here. This +3.3V supply must be well decoupled

and filtered for good noise immunity since the audio performance of the device depends

upon the PLL circuit.

I/O

GND_CLEAN

Reference ground

I/O

GND_REG

Substrate ground

I/O

VDD_REG

Logic supply

I/O

Logic supply to power section

CONFIG

Logic levels

RESET

Reset

SCL

I2C serial clock

I/O

SDA

I2C serial data

RESERVED

Reserved test pin must be connected to ground

PLL_FILTER

Connection to PLL filter

XTI

PLL input clock

I/O

GNDA

Analog ground

I/O

VDDA

Analog supply 3.3

SDI_12

I2S serial data channels 1 and 2

I/O

LRCKI

I2S left/right clock,

BICKI

I2S serial clock

I/O

GND

Digital ground

I/O

VDD

Digital supply 3.3 V

I/O

VSS

5 V regulator referred to Vcc

I/O

VCC_SIGN

5 V regulator referred to ground

Table 5.

Pin list (continued)

Type

Name

Description

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