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STV2310 데이터시트(PDF) 78 Page - STMicroelectronics

부품명 STV2310
상세설명  Multistandard TV Digital Video Decoder with Adaptive Comb Filter and RGB/YCrCb Input
PDF  112 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STV2310 데이터시트(HTML) 78 Page - STMicroelectronics

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Register List
STV2310
78/112
DDECCONT28
Register Description
DDECCONT29
Register Description
DDECCONT2A
Register Description
Address (hex): 28h
Reset Value (bin): 1000 0010
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HUNLOCK_LINE_NUM[3:0]
HLOCK_LINE_NUM[3:0]
Bit Name
Function
HUNLOCK_LINE
_NUM[3:0]
HPLL number/4 of successive err>thresh for hunlock
This register is used by the HPLL. It provides the number of successive lines divided by 4 where the phase
error must be above the required threshold to consider the hlock to be lost. The default value is 8 x 4 lines.
HLOCK_LINE_N
UM
[3:0]
HPLL number/4 of successive err<thresh for hlock
This register is used by the HPLL. Its entry is the number of successive lines divided by 4 where the phase
error must be below the required threshold before the hlock is acquired (a value of 0001 h = 1 means 4
lines). The default value is 2 x 4 lines.
Address (hex): 29h
Reset Value (bin): 0101 0101
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HLOCK_PH_ER_TH[3:0]
Bit Name
Function
Bit 7
Reserved. Must be set to 0.
Bit 7
Reserved. Must be set to 1.
Bits [5:4]
Reserved. Must be set to 01.
HLOCK_PH_ER_
TH[3:0]
HPLL phase error threshold / 8 for hlock / hunlock
This register provides the phase error threshold for the HPLL. The same value is used for the lock and
unlock mechanism. The entry value is the number of samples multiplied by 8. The default value is 5 x 8
samples.
Address (hex): 2Ah
Reset Value (bin): 1000 0010
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLAMP_PROP[1:0]
CLAMP_DER[1:0]
CLAMP_INT[2:0]



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