STW8009 datasheet(28/66 Pages) STMICROELECTRONICS

28 / 66 page

STw8009/STw8019

Control registers

27/65

setup_main: pedestal

0 = Blanking level and black level are identical on all lines.

(e.g.: Argentinian PAL-N, Japan NTSC-M, PAL-BDGHI)

(*) 1 = Black level is 7.5 IRE above blanking level on all lines outside VBI

(e.g. Paraguayan and Uruguayan PAL-N).

In all cases, gain factor is adjusted to obtain the required levels for chrominance.

Note:

Depending on the different output configurations chosen by programming bit from

dac12_conf, pedestal is automatically selected on it.

nintrl: non-interlaced mode select

(*) 0 = interlaced mode (625/50 or 525/60 system)

1 = non-interlaced mode(2x312/50 or 2x262/60 system)

enrst: cyclic update of DDFS phase

(*) 0 = no cyclic subcarrier phase reset

1 = cyclic subcarrier phase reset depending of valrst1 and valrst0 (see below)

bursten: chrominance burst control

0 = burst is turned off on CVBS, chrominance output is not affected

(*) 1 = burst is enabled

selrst: selects set of reset values for Direct Digital Frequency Synthesizer accumulator

(*) 0 = hardware reset values for phase of subcarrier oscillator (see description of

registers 13 and14 for values)

1 = loaded reset values selected (see contents of registers 13 and 14)

rstosc_buf: software phase reset of DDFS (Direct Digital Frequency Synthesizer) buffer

(*) 0

1 = when a 0-to-1 transition occurs either the hard-wired default phase value or the

value loaded in Reg. 13-14 (according to bit ‘selrst’) is put to the phase buffer. This

value is then loaded into accumulator (phase of sub-carrier) when the bits

‘ph_rst_mode’ from register 8 are programmed or when standard changes or when a

soft reset occur.

Note:

Bit ‘rstosc_buf’ is automatically set back to ‘0’ after the buffer is loaded.

valrst [1:0]

Note: valrst[1:0] is taken into account only if bit ‘enrst’ is set.

configuration2

Address: 0x0002

Type: R/W

content

nintrl

enrst

bursten

xxx

selrst

rstosc_

buf

valrst1

valrst0

default

1000

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