STW8009 datasheet(41/66 Pages) STMICROELECTRONICS

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Control registers

STw8009/STw8019

40/65

main_del[3:0]: delay on chroma path with reference to luma path, on the encoded signal

coming from the main outputs. The delay value varies with modes, delays are hardwired to

have different delays in different modes. If the delays are to be made programmable, set bit

main_del_en to 1 (Reg 03) to enable soft delay from main_del[3:0].

If main_del_en = 0 then the delays used are:

Bit flt_ys enables the software loading capability of luma coefficients. Values from registers

82 to 91 are used only when bit “flt_ys” of this register is set to 1. Bit “flt_ys” has the highest

priority. With this bit set to 1, all bits from plg_div_y[1:0] must be programmed as luma

coefficients. Alternatively, the default values of the coefficients are loaded. The luma

coefficients are mode and standard independent.

flt_ys default value is “0”.

Configuration 9

Address:

0x0051

Type: R/W

content

main_de

xxx

plg_div_

flt_ys

default

1000

Table 16.

main_del[3:0]

main_

del3

main_

del2

main_

del1

main_

del0

Delay on chroma path with reference to luma path

encoding [One pixel corresponds to 2/

fpix_clk]

(*)

0010

- 0.5 pixel delay on chroma

0011

- 1 pixel delay on chroma

0100

- 1.5 pixel delay on chroma

0101

- 2 pixel delay on chroma

1100

+ 2.5 pixel delay on chroma

1101

+ 2 pixel delay on chroma

1110

+ 1.5 pixel delay on chroma

1111

+ 1 pixel delay on chroma

Others

0 pixel delay on chroma (reference delay)

Others

+ 0.5 pixel delay on chroma

main_del[3:0] = 0010 when mode = PAL/NTSC in 4:2:2 format on CVBS

main_del[3:0] = 0001 when mode = PAL/NTSC in 4:4:4.

plg_div_y = 00 when sum of coefficients = 256

plg_div_y = 01 when sum of coefficients = 512 (default)

plg_div_y = 10 when sum of coefficients = 1024

plg_div_y = 11 when sum of coefficients = 2048

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