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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M306V2EEFS 데이터시트(PDF) 67 Page - Renesas Technology Corp |
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M306V2EEFS 데이터시트(HTML) 67 Page - Renesas Technology Corp |
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67 / 271 page  Rev.1.40 Oct 06, 2004 page 67 of 269 M306V2ME-XXXFP, M306V2EEFP 2.8 Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK , bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK , the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer’s period can be calcu- lated as given below. The watchdog timer’s period is, however, subject to an error due to the pre-scaler. With XIN chosen for BCLK Watchdog timer period = With XCIN chosen for BCLK Watchdog timer period = For example suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the pre-scaler, then the watchdog timer’s period becomes approximately 52.4 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). Figure 2.8.1 shows the block diagram of the watchdog timer. Figure 2.8.2 shows the watchdog timer control register and Figure 2.8.3 shows the watchdog timer start register. pre-scaler dividing ratio (16 or 128) ✕ watchdog timer count (32768) BCLK pre-scaler dividing ratio (2) ✕ watchdog timer count (32768) BCLK |
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