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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M306V2EEFS 데이터시트(PDF) 170 Page - Renesas Technology Corp |
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M306V2EEFS 데이터시트(HTML) 170 Page - Renesas Technology Corp |
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170 / 271 page  Rev.1.40 Oct 06, 2004 page 170 of 269 M306V2ME-XXXFP, M306V2EEFP 2.14.5 Timing Signal Generating Circuit This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal syn- chronous signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer control register 1 (address 026016) to “1.” The reference clock can be used as a display clock for OSD function in addition to the data slicer. The HSYNC signal can be used as a count source instead of the composite sync signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 026016). For the pins HLF, connect a resistor and a capacitor as shown in Figure 2.14.1 Make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be generated. Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. In this period, various timing signals, Hsep signals and Vsep signals become unstable. For this reason, take stabilization time into consideration when programming. Figure 2.14.7 Determination of v-pulse waveform Composite sync signal A B 0 1 1 Bit 5 of DSC2 |
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