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M306V2EEFS 데이터시트(PDF) 186 Page - Renesas Technology Corp

부품명 M306V2EEFS
상세설명  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PDF  271 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M306V2EEFS 데이터시트(HTML) 186 Page - Renesas Technology Corp

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Rev.1.40
Oct 06, 2004 page 186 of 269
M306V2ME-XXXFP, M306V2EEFP
The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC).
At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising
edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So
interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs
enough time (2 ✕ BCLK cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can
select with the I/O polarity control register (address 020616).
Figure 2.16.9 Supplement explanation for display position
When bits 0 and 1 of the I/O polarity control register
(address 020616) are set to “1” (negative polarity)
VSYNC signal input
VSYNC control
signal in
microcomputer
0.1 to 0.2 [
µs]
(BCLK = 10 MHz)
Period of counting
HSYNC signal
(Note 2)
HSYNC
signal input
Not count
12345
Notes 1 : The vertical position is determined by counting falling edge of
HSYNC signal after rising edge of VSYNC control signal in the
microcomputer.
2: Do not generate falling edge of HSYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
3: The pulse width of HSYNC needs 26 ✕ BCLK cycles or more
(BCLK = 10 MHz).
8 ✕ BCLK cycles or more
26 ✕ BCLK cycles
or more



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