R8C2K datasheet(354/471 Pages) RENESAS

354 / 471 page

R8C/2K Group, R8C/2L Group

18. Hardware LIN

Rev.1.10

Dec 21, 2007

Page 337 of 450

REJ09B0406-0110

18.4

Functional Description

18.4.1

Master Mode

Figure 18.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.

Figures 18.5 and 18.6 show an Example of Header Field Transmission Flowchart.

When transmitting a header field, the hardware LIN operates as described below.

(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware

LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for timer

RA.

(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of the

TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the LINCR

(3) The hardware LIN transmits 55h via UART0.

(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.

(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.

Figure 18.4

Typical Operation when Sending a Header Field

TXD0 pin

Synch Break

SBDCT flag in the

LINST register

IR bit in the TRAIC

Synch Field

IDENTIFIER

(1)

(2)

(3)

(4)

(5)

Set by writing 1 to the

B1CLR bit in the LINST

Cleared to 0 upon

acceptance of interrupt

request or by a program

The above applies under the following conditions:

LINE = 1, MST = 1, SBIE = 1

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