R8C2K datasheet(61/471 Pages) RENESAS

61 / 471 page

R8C/2K Group, R8C/2L Group

6. Voltage Detection Circuit

Rev.1.10

Dec 21, 2007

Page 44 of 450

REJ09B0406-0110

Figure 6.11

Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation

Vdet2

VCA13 bit

Internal reset signal

(VW2C6 = 1)

VCC

The above applies under the following conditions.

• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)

• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled)

NOTE:

1. When voltage monitor 0 reset is not used, set the power supply to VCC

≥ 2.2.

2.2 V(1)

4 cycles of sampling clock of

digital filter

VW2C2 bit

When the VW2C1 bit is set

to 0 (digital filter enabled)

VW2C2 bit

When the VW2C1 bit is

set to 1 (digital filter

disabled) and the

VW2C7 bit is set to 0

(Vdet2 or above)

VCA13: Bit in VCA1 register

VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register

Set to 0 by interrupt request

acknowledgement

Set to 0 by a program

Voltage monitor 2

interrupt request

(VW2C6 = 0)

Voltage monitor 2

interrupt request

(VW2C6 = 0)

VW2C2 bit

When the VW2C1 bit is

set to 1 (digital filter

disabled) and the

VW2C7 bit is set to 1

(Vdet2 or below)

Voltage monitor 2

interrupt request

(VW2C6 = 0)

Internal reset signal

(VW2C6 = 1)

4 cycles of sampling clock of

digital filter

Set to 0 by a program

Set to 0 by interrupt

request

acknowledgement

Set to 0 by a program

Set to 0 by interrupt

request acknowledgement

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