R8C2K datasheet(62/471 Pages) RENESAS

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R8C/2K Group, R8C/2L Group

7. Programmable I/O Ports

Rev.1.10

Dec 21, 2007

Page 45 of 450

REJ09B0406-0110

Programmable I/O Ports

There are 25 programmable Input/Output ports (I/O ports) P0_0 to P0_3, P0_5, P1, P2, P3_3 to P3_5, P4_5. Also, if

the XIN clock oscillation circuit is not used, P4_6 and P4_7 can be used as input-only ports. If the A/D converter is not

used, P4_2 can be used as an input-only port.

Table 7.1 lists an Overview of Programmable I/O Ports.

NOTES:

1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers

PUR0, and PUR1.

2. When the XIN clock oscillation circuit is not used, these ports can be used as the input-only ports.

7.1

Functions of Programmable I/O Ports

The PDi_j (j = 0 to 7) bit in the PDi (i = 0 to 4) register controls I/O of the ports P0_0 to P0_3, P0_5, P1, P2, P3_3

to P3_5, P4_5. The Pi register consists of a port latch to hold output data and a circuit to read pin states.

Figures 7.1 to 7.6 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of

Programmable I/O Ports. Also, Figure 7.8 shows the PDi (i = 0 to 4) Registers. Figure 7.9 shows the Pi (i = 0 to 4)

Registers, Figure 7.10 shows the P2DRR Register, Figure 7.11 shows Registers PINSR1, PINSR2, PINSR3, and

PMR, Figure 7.12 shows Registers PUR0, and PUR1.

i = 0 to 4, j = 0 to 7

NOTE:

1. Nothing is assigned to the following bits:

PD0_4, PD0_6, PD0_7, PD3_0 to PD3_2, PD3_6, PD3_7, PD4_0 to PD4_4, PD4_6, PD4_7

Table 7.1

Overview of Programmable I/O Ports

Ports

I/O

Type of Output

I/O Setting

Internal Pull-Up Resister

P0_0 to P0_3, P1, P2

I/O

CMOS3 State

Set per bit

Set every 4 bits(1)

P3_4, P3_5

I/O

CMOS3 State

Set per bit

Set every 2 bits(1)

P0_5, P3_3, P4_5

I/O

CMOS3 State

Set per bit

Set every bit(1)

P4_2, P4_6(2), P4_7(2)

(No output function)

None

Table 7.2

Functions of Programmable I/O Ports

Operation When

Accessing

Pi Register

Value of PDi_j Bit in PDi Register(1)

When PDi_j Bit is Set to 0 (Input Mode)

When PDi_j Bit is Set to 1 (Output Mode)

Reading

Read pin input level

Read the port latch

Writing

Write to the port latch

Write to the port latch. The value written to

the port latch is output from the pin.

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