R8C2K datasheet(59/471 Pages) RENESAS

59 / 471 page

R8C/2K Group, R8C/2L Group

6. Voltage Detection Circuit

Rev.1.10

Dec 21, 2007

Page 42 of 450

REJ09B0406-0110

Figure 6.10

Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation

Vdet1

VW1C3 bit

Internal reset signal

(VW1C6 = 1)

VCC

The above applies under the following conditions.

• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)

• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled)

NOTE:

1. If voltage monitor 0 reset is not used, set the power supply to VCC

≥ 2.2.

2.2 V(1)

4 cycles of sampling clock of

digital filter

VW1C2 bit

When the VW1C1 bit is set

to 0 (digital filter enabled)

VW1C2 bit

When the VW1C1 bit is

set to 1 (digital filter

disabled) and the

VW1C7 bit is set to 0

(Vdet1 or above)

VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bit in VW1C Register

Set to 0 by interrupt request

acknowledgement

Set to 0 by a program

Voltage monitor 1

interrupt request

(VW1C6 = 0)

Voltage monitor 1

interrupt request

(VW1C6 = 0)

VW1C2 bit

When the VW1C1 bit is

set to 1 (digital filter

disabled) and the

VW1C7 bit is set to 1

(Vdet1 or below)

Voltage monitor 1

interrupt request

(VW1C6 = 0)

Internal reset signal

(VW1C6 = 1)

4 cycles of sampling clock of

digital filter

Set to 0 by a program

Set to 0 by interrupt

request

acknowledgement

Set to 0 by a program

Set to 0 by interrupt

request acknowledgement

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