| 전자부품 데이터시트 검색엔진 |
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R8C2K 데이터시트(PDF) 197 Page - Renesas Technology Corp |
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R8C2K 데이터시트(HTML) 197 Page - Renesas Technology Corp |
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197 / 471 page ![]() R8C/2K Group, R8C/2L Group 16. Timers Rev.1.10 Dec 21, 2007 Page 180 of 450 REJ09B0406-0110 Figure 16.32 TRCSR Register Timer RC Status Register Symbol Address After Reset TRCSR 0123h 01110000b Bit Symbol Bit Name Function RW NOTE: 1. — (b6-b4) — Nothing is assigned. If necessary, set to 0. When read, the content is 1. RW OVF Overflow flag [Source for setting this bit to 0] Write 0 after read(1). [Source for setting this bit to 1] Refer to the table below . Input capture / compare match flag C IMFC RW [Source for setting this bit to 0] Write 0 after read(1). [Source for setting this bit to 1] Refer to the table below . RW Input capture / compare match flag D RW IMFB RW Input capture / compare match flag A Input capture / compare match flag B IMFA b7 b6 b5 b4 The w riting results are as follow s: • This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. • This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) • This bit remains unchanged if 1 is w ritten to it. b3 b2 IMFD b1 b0 Input capture Function Output Compare Function TRCIOA pin input edge(1) TRCIOB pin input edge(1) TRCIOC pin input edge(1) TRCIOD pin input edge(1) NOTES: 1. 2. IMFA OVF Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and TRCGRB). PWM2 Mode When the TRC register overflow s. When the values of the registers TRC and TRCGRA match. When the values of the registers TRC and TRCGRB match. Timer Mode PWM Mode Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D). Bit Symbol When the values of the registers TRC and TRCGRC match.(2) When the values of the registers TRC and TRCGRD match.(2) IMFB IMFC IMFD |
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