R8C2K datasheet(205/471 Pages) RENESAS

205 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 188 of 450

REJ09B0406-0110

Figure 16.41

Buffer Operation for Output Compare Function

Make the following settings in timer mode.

• To use the TRCGRC register as the buffer register for the TRCGRA register:

Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.

• To use the TRCGRD register as the buffer register for the TRCGRB register:

Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.

The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is

functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare

match with the TRC register occurs.

The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,

the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin

or TRCIOD pin.

TRCGRA register

m-1

m+1

TRC register

The above applies under the following conditions:

• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).

• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match).

Transfer

TRCGRC register

(buffer)

TRCIOA output

TRCGRC

TRCGRA

Comparator

TRC

Compare match signal

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