R8C2K datasheet(224/471 Pages) RENESAS

224 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 207 of 450

REJ09B0406-0110

Figure 16.56

Operating Example of PWM Mode (Duty 0% and Duty 100%)

Rewritten by

a program

TRC register value

m: TRCGRA register setting value

Set to 0 by a program

Rewritten by a program

0000h

Duty 0%

TRCGRB register

IMFA bit in

TRCSR register

IMFB bit in

TRCSR register

TSTART bit in

TRCMR register

TRCIOB output

p (p>m)

TRC register value

0000h

TRCGRB register

IMFA bit in

TRCSR register

IMFB bit in

TRCSR register

TSTART bit in

TRCMR register

TRCIOB output

The above applies under the following conditions:

• The EB bit in the TRCOER register is set to 0 (output from TRCIOB enabled).

• The TOB bit in the TRCCR1 register is set to 1 (active level is “L”).

TRCIOB output does not switch to “L” because

no compare match with the TRCGRB register

has occurred

If compare matches occur simultaneously with registers TRCGRA and

TRCGRB, the compare match with the TRCGRB register has priority.

TRCIOB output switches to “L”. (In other words, no change).

TRCIOB output switches to “L” at compare match with the

TRCGRB register. (In other words, no change).

Set to 0 by a program

Duty 100%

Set to 0 by a program

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