R8C2K datasheet(242/471 Pages) RENESAS

242 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 225 of 450

REJ09B0406-0110

16.4.4

Pulse Output Forced Cutoff

In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode, and

PWM3 mode, the TRDIOji (i = 0 or 1, j = either A, B, C, or D) output pin can be forcibly set to a programmable

I/O port by the INT0 pin input, and pulse output can be cut off.

The pins used for output in these functions or modes can function as the output pin of timer RD when the

applicable bit in the TRDOER1 register is set to 0 (enable timer RD output). When the PTO bit in the

TRDOER2 register to 1 (INT0 of pulse output forced cutoff signal input enabled), all bits in the TRDOER1

after “L” is applied to the INT0 pin. The TRDIOji output pin is set to the programmable I/O port after “L” is

applied to the INT0 pin and waiting for 1 to 2 cycles of the timer RD operation clock (refer to Table 16.25

Timer RD Operation Clocks).

Set as below when using this function:

• Set the pin status (high impedance, “L” or “H” output) to pulse output forced cutoff by registers P2 and

PD2.

• Set the INT0EN bit in the INTEN register to 1 (enable INT0 input) and the INT0PL bit to 0 (one edge).

• Set the PD4_5 bit in the PD4 register to 0 (input mode).

• Set the INT0 digital filter by bits INT0F1 to INT0F0 in the INTF register.

• Set the PTO bit in the TRDOER2 register to 1 (enable pulse output forced cutoff signal input INT0).

According to the selection of the POL bit in the INT0IC register and change of the INT0 pin input, the IR bit in

the INT0IC register is set to 1 (interrupt request). Refer to 12. Interrupts for details of interrupts.

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