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R8C2K 데이터시트(PDF) 268 Page - Renesas Technology Corp

부품명 R8C2K
상세설명  RENESAS MCU R8C FAMILY / R8C/2x SERIES
PDF  471 Pages
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제조업체  RENESAS [Renesas Technology Corp]
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R8C2K 데이터시트(HTML) 268 Page - Renesas Technology Corp

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R8C/2K Group, R8C/2L Group
16. Timers
Rev.1.10
Dec 21, 2007
Page 251 of 450
REJ09B0406-0110
Figure 16.92
Registers TRDSR0 to TRDSR1 in Output Compare Function
Timer RD Status Register i (i=0 or 1)
Symbol
Address
After Reset
TRDSR0
TRDSR1
0143h
0153h
11100000b
11000000b
Bit Symbol
Bit Name
Function
RW
NOTES:
1.
2.
3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
b3 b2
IMFD
b1 b0
b7 b6 b5 b4
RW
IMFB
RW
Input capture/compare match
flag A
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
Input capture/compare match
flag B
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
IMFA
Input capture/compare match
flag C
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRCi register(3).
Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
IMFC
RW
RW
Input capture/compare match
flag D
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRDi register(3).
Overflow flag
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRDi register overflow s.
—
(b7-b6)
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
OVF
UDF
Underflow flag(1)
This bit is disabled in the output compare function.
RW



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