R8C2K datasheet(304/471 Pages) RENESAS

304 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 287 of 450

REJ09B0406-0110

Figure 16.127 Registers TRDCR0 to TRDCR1 in Complementary PWM Mode

Timer RD Control Register i (i = 0 or 1)

Symbol

Address

After Reset

TRDCR0

TRDCR1

0140h

0150h

00h

Bit Symbol

Bit Name

Function

NOTES:

3. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the

TRDFCR register is set to 1 (external clock input enabled).

CKEG1

CCLR0

Set to 000b (disable clearing (free-running

operation)) in complementary PWM mode.

TRDi counter clear select bits

This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).

Set bits TCK2 to TCK0 and bits CKEG1 to CKEG0 in registers TRDCR0 and TRDCR1 to the same values.

b3 b2

CKEG0

b1 b0

TCK2

000

b7 b6 b5 b4

CCLR2

CCLR1

Count source select bits(2)

b2 b1 b0

0 0 0 : f1

0 0 1 : f2

0 1 0 : f4

0 1 1 : f8

1 0 0 : f32

1 0 1 : TRDCLK input(1)

1 1 0 : fOCO40M

1 1 1 : Do not set.

External clock edge select bits(2,3)

b4 b3

0 0 : Count at the rising edge

0 1 : Count at the falling edge

1 0 : Count at both edges

1 1 : Do not set.

TCK1

TCK0

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