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AFE5804 데이터시트(PDF) 6 Page - Texas Instruments |
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AFE5804 데이터시트(HTML) 6 Page - Texas Instruments |
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6 / 60 page ![]() DIGITAL CHARACTERISTICS AFE5804 SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level '0' or '1'. At CLOAD = 5pF (1), I OUT = 3.5mA (2), R LOAD = 100Ω (2), and no internal termination, unless otherwise noted. AFE5804 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 1.4 3.3 V Low-level input voltage 0 0.3 V High-level input current 10 µA Low-level input current(3) –10 µA Input capacitance 3 pF LVDS OUTPUTS High-level output voltage 1375 mV Low-level output voltage 1025 mV Output differential voltage, |VOD| 350 mV VOS output offset voltage (2) Common-mode voltage of OUTP and OUTM 1200 mV Output capacitance inside the device, from either Output capacitance 2 pF output to ground 1x (clock FCLKP and FCLKM 10 50 MHz rate) 6x (clock LCLKP and LCLKM 60 300 MHz rate) CLOCK Clock input rate 10 50 MSPS Clock duty cycle 50 % Clock input amplitude, differential Sine-wave, ac-coupled 3 VPP (VCLKP – VCLKM) LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP Clock input amplitude, single-ended (VCLKP) High-level input voltage, VIH CMOS 2.2 V Low-level input voltage, VIL CMOS 0.6 V (1) CLOAD is the effective external single-ended load capacitance between each output pin and ground. (2) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. (3) Except pin J3 (INT/EXT), which has an internal pull-up resistor (52k Ω) to 3.3V. 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): AFE5804 |
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