| 전자부품 데이터시트 검색엔진 |
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M16C/29 데이터시트(PDF) 335 Page - Renesas Technology Corp |
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M16C/29 데이터시트(HTML) 335 Page - Renesas Technology Corp |
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335 / 499 page ![]() 17. CAN Module p u o r G 9 2 / C 6 1 M page 311 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R 17.10.2 Transmission Figure 17.26 shows the timing of the transmit sequence. CTx TrmReq bit TrmActive bit CAN0 Successful Transmission Interrupt TrmState bit TrmSucc bit MBOX bit SentData bit SOF SOF Transmission slot No. EOF IFS (1) (2) (2) (1) (1) (3) (4) (3) (3) j = 0 to 15 ACK Figure 17.26 Timing of Transmit Sequence (1) If the TrmReq bit in the C0MCTLj register (j = 0 to 15) is set to 1 (Transmission slot) in the bus idle state, the TrmActive bit in the C0MCTLj register and the TrmState bit in the C0STR register are set to 1 (Transmitting/Transmitter), and CAN module starts the transmission. (2) If the arbitration is lost after the CAN module starts the transmission, the TrmActive and TrmState bits are set to 0. (3) If the transmission has been successful without lost in arbitration, the SentData bit in the C0MCTLj register is set to 1 (Transmission is successfully completed) and TrmActive bit in the C0MCTLj register is set to 0 (Waiting for bus idle or completion of arbitration). And when the interrupt enable bits in the C0ICR register = 1 (Interrupt enabled), CAN0 successful transmission interrupt request is generated and the MBOX (the slot number which transmitted the message) and TrmSucc bit in the C0STR register are changed. (4) When starting the next transmission, set bits SentData and TrmReq to 0. And set the TrmReq bit to 1 after checking that bits SentData and TrmReq are set to 0. |
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