전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

M16C/29 데이터시트(PDF) 335 Page - Renesas Technology Corp

부품명 M16C/29
상세설명  RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
PDF  499 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M16C/29 데이터시트(HTML) 335 Page - Renesas Technology Corp

Back Button M16C/29 Datasheet HTML 331Page - Renesas Technology Corp M16C/29 Datasheet HTML 332Page - Renesas Technology Corp M16C/29 Datasheet HTML 333Page - Renesas Technology Corp M16C/29 Datasheet HTML 334Page - Renesas Technology Corp M16C/29 Datasheet HTML 335Page - Renesas Technology Corp M16C/29 Datasheet HTML 336Page - Renesas Technology Corp M16C/29 Datasheet HTML 337Page - Renesas Technology Corp M16C/29 Datasheet HTML 338Page - Renesas Technology Corp M16C/29 Datasheet HTML 339Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 335 / 499 page
background image
17. CAN Module
p
u
o
r
G
9
2
/
C
6
1
M
page 311
8
5
4
f
o
7
0
0
2
,
0
3
.r
a
M
2
1
.
1
.
v
e
R
2
1
1
0
-
1
0
1
0
B
9
0
J
E
R
17.10.2 Transmission
Figure 17.26
shows the timing of the transmit sequence.
CTx
TrmReq bit
TrmActive bit
CAN0 Successful
Transmission Interrupt
TrmState bit
TrmSucc bit
MBOX bit
SentData bit
SOF
SOF
Transmission slot No.
EOF
IFS
(1)
(2)
(2)
(1)
(1)
(3)
(4)
(3)
(3)
j = 0 to 15
ACK
Figure 17.26 Timing of Transmit Sequence
(1) If the TrmReq bit in the C0MCTLj register (j = 0 to 15) is set to 1 (Transmission slot) in the bus idle
state, the TrmActive bit in the C0MCTLj register and the TrmState bit in the C0STR register are set to
1 (Transmitting/Transmitter), and CAN module starts the transmission.
(2) If the arbitration is lost after the CAN module starts the transmission, the TrmActive and TrmState bits
are set to 0.
(3) If the transmission has been successful without lost in arbitration, the SentData bit in the C0MCTLj
register is set to 1 (Transmission is successfully completed) and TrmActive bit in the C0MCTLj register
is set to 0 (Waiting for bus idle or completion of arbitration). And when the interrupt enable bits in the
C0ICR register = 1 (Interrupt enabled), CAN0 successful transmission interrupt request is generated
and the MBOX (the slot number which transmitted the message) and TrmSucc bit in the C0STR
register are changed.
(4) When starting the next transmission, set bits SentData and TrmReq to 0. And set the TrmReq bit to
1 after checking that bits SentData and TrmReq are set to 0.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com