M16CSLASH29 datasheet(218/499 Pages) RENESAS

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14.Serial I/O

page 194

Transfer clock

“H”

“L”

PSP

TxD2

(no reverse)

“H”

“L”

TxD2

(reverse)

“H”

“L”

(1) When the U2LCH bit in the U2C1 register is set to 0 (no reverse)

(2) When the U2LCH bit in the U2C1 register is set 1 (reverse)

Transfer clock

“H”

“L”

NOTE:

1. This applies to the case where the CKPOL bit in the U2C0 register is set to 0

(transmit data output at the falling edge of the transfer clock), the UFORM bit in

the U2C0 register is set to 0 (LSB first), the STPS bit in the U2MR register is set

to 0 (1 stop bit) and the PRYE bit in the U2MR register is set to 1 (parity

ST: Start bit

P: Parity bit

SP: Stop bit

(1) When the IOPOL bit in the U2MR register is set to 0 (no reverse)

(2) When the IOPOL bit in the U2MR register is set to 1 (reverse)

ST: Start bit

P: Parity bit

SP: Stop bit

PSP

“H”

Transfer clock

TxD2

(no reverse)

RxD2

(no reverse)

Transfer clock

TxD2

(reverse)

RxD2

(reverse)

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

NOTE:

1. This applies to the case where the UFORM bit in the U2C0 register is set

to 0 (LSB first), the STPS bit in the U2MR register is set to 0 (1 stop bit)

and the PRYE bit in the U2MR register is set to 1 (parity enabled).

14.1.2.4 Serial Data Logic Switching Function (UART2)

The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the

received data has its logic reversed when read from the U2RB register. Figure 14.19 shows serial

data logic.

Figure 14.19 Serial Data Logic Switching

14.1.2.5 TxD and RxD I/O Polarity Inverse Function (UART2)

This function inverses the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all

input/output data (including the start, stop and parity bits) are inversed. Figure 14.20 shows the TXD

pin output and RXD pin input polarity inverse.

Figure 14.20 TXD and RXD I/O Polarity Inverse

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