| 전자부품 데이터시트 검색엔진 |
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M16C/29 데이터시트(PDF) 221 Page - Renesas Technology Corp |
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M16C/29 데이터시트(HTML) 221 Page - Renesas Technology Corp |
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221 / 499 page ![]() 14. Serial I/O p u o r G 9 2 / C 6 1 M page 197 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 14.22 I2C bus mode Block Diagram CLK control Falling edge detection External clock Internal clock Start/stop condition detection interrupt request Start condition detection Stop condition detection Reception register Bus busy Transmission register Arbitration Noise Filter SDA2 SCL2 UART2 D T Q D T Q D T Q NACK ACK UART2 UART2 UART2 R UART2 transmit, NACK interrupt request UART2 receive, ACK interrupt request, DMA1 request IICM=1 and IICM2=0 S R Q ALS R S SWC IICM=1 and IICM2=0 IICM2=1 IICM2=1 SWC2 SDHI DMA0, DMA1 request Noise Filter IICM=0 IICM=1 DMA0 STSPSEL=0 STSPSEL=1 STSPSEL=1 STSPSEL=0 SDASTSP SCLSTSP ACKC=1 ACKC=0 Q Port register (1) I/O port 9th bit falling edge 9th bit ACKD bit Delay circuit Start and stop condition generation block This diagram applies to the case where bits SMD2 to SMD0 in the U2MR register is set to 0102 and the IICM bit in the U2SMR register is set to 1. IICM: Bit in the U2SMR register IICM2, SWC, ALS, SWC2, SDHI: Bits in the U2SMR2 register STSPSEL, ACKD, ACKC: Bits in the U2SMR4 register NOTE: 1. If the IICM bit is set to 1, the pin can be read even when the PD7_1 bit is set to 1 (output mode). |
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