M32CSLASH8B datasheet(328/406 Pages) RENESAS

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Under development

M32C/8B Group

23. Flash Memory

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 311 of 385

23.6.1.1

Software Commands

Write commands or read and write data to the specified even addresses in the user ROM area in 16-bit units.

When writing a command code, 8 high-order bits (D15 to D8) are ignored.

Table 23.5

Software Commands

FA: Any even address in the user ROM area

WA0: 16 low-order bits of write address

• Set the lowest 2-bit of the address to 00b.

• The address specified in the first bus cycle is the same even address as the write address specified in the

second bus cycle.

WA1: 16 high-order bits of write address

• Set the lowest 2-bit of the address to 10b.

• Specify WA0 and WA1 in the consecutive even addresses.

BA0: Highest-order even address of a block

BA1: Any even address of a block

PBA: The protect bit address (See table 23.2)

WD0: 16 low-order bit of write data

WD1: 16 high-order bit of write data

RD0: Read data (bit 6 is the lock bit data)

RD1: Read data (bit 6 is the protect bit data)

SRD: Data in the Status Register (b7 to b0)

xx: 8 high-order bits of command code (ignored)

NOTES:

1. When the FMR31 bit in the FMR3 register is set to 1 (read by the FMR16 bit in the FMR1 register).

2. When the FMR31 bit in the FMR3 register is set to 0 (read via the data bus).

(1) Read Array Command

The read array command is used to read the flash memory.

The flash memory enters read array mode when the command code xxFFh is written in the first bus cycle. The

content of the specified address can be read in 16-bit units when a read address is specified after the next bus

cycle. The flash memory remains in read array mode until the other command is written. Therefore, the contents

of multiple addresses can be read in succession.

(2) Read Status Register Command

The read status register command is used to read the Status Register. When the command code xx70h is written

in the first bus cycle, the Status Register can be read after the second bus cycle (refer to 23.6.1.2 Status

this command in EW1 mode.

Software Command

First Bus Cycle

Second Bus Cycle

Third Bus Cycle

Mode Address

Data

(D15 to D0)

Mode Address

Data

(D15 to D0)

Mode Address

Data

(D15 to D0)

Read array

Write

xxFFh

−−

−

Read status register

Write

xx70h

Read

SRD

−−

−

Clear status register

Write

xx50h

−−

−

Program

Write

WA0

xx41h

Write

WA0

WD0

Write

WA1

WD1

Block erase

Write

xx20h

Write

BA0

xxD0h

−−

−

Lock bit program

Write

BA0

xx77h

Write

BA0

xxD0h

−−

−

Read lock bit status(1)

Write

xx71h

Write

BA0

xxD0h

−−

−

Read lock bit status(2)

Write

xx71h

Read

BA1

RD0

−−

−

Protect bit program

Write

PBA

xx67h

Write

PBA

xxD0h

−−

−

Read protect bit status Write

xx61h

Read

PBA

RD1

−−

−

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